Vector Computer Memory Bank Contention
IEEE Transactions on Computers
Some results in memory conflict analysis
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Memory conflicts and machine performance
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Measurement of memory access contentions in multiple vector processor systems
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Access conflicts in multiprocessor memories queueing models and simulation studies
ICS '90 Proceedings of the 4th international conference on Supercomputing
Mean-Value Analysis of Closed Multichain Queuing Networks
Journal of the ACM (JACM)
The Operational Analysis of Queueing Network Models
ACM Computing Surveys (CSUR)
Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
Mean Value Analysis fo Queueing Networks - A New Look at an Old Problem
Proceedings of the Third International Symposium on Modelling and Performance Evaluation of Computer Systems: Performance of Computer Systems
Measurement of memory access contentions in multiple vector processor systems
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Memory contention for shared memory vector multiprocessors
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Characterizing the Performance of Algorithms for Lock-Free Objects
IEEE Transactions on Computers
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
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The performance of an interleaved common memory accessed uniformly by multiple processors is modeled by queuing and simulation methods. The model includes access conflicts at the bank level while assuming an ideal access network. A general scaling law is derived that indicates that memory access delays are given by the product of the bank reservation time and a function of the memory utilization, which is the average number of access requests arriving at a bank per bank reservation time. For light, uniform memory traffic, access delays are proportional to the square of the bank reservation time and to the ratio of the number of active memory access streams to the number of memory banks. With an assumption of random access patterns, an open and a closed queuing model are developed. To model pipelined access operations a new negative feedback model is introduced that includes the open and the closed models as special cases and is also well suited for modeling linked access streams. Delay dependence on bank reservation time is quadratic for light loads and linear for very heavy loads. The queuing models are validated by simulations.