Scientific computing on vector computers
Scientific computing on vector computers
Analysis of determinant factors for the performance of vector machines
INRIA Conference on Supercomputing: state-of-the-art
A Guidebook to FORTRAN on Supercomputers
A Guidebook to FORTRAN on Supercomputers
Memory contention for shared memory vector multiprocessors
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
A Memory Interference Model for Regularly Patterned Multiple Stream Vector Accesses
IEEE Transactions on Parallel and Distributed Systems
Matrix Partitioning on a Virtual Shared Memory Parallel Machine
IEEE Transactions on Parallel and Distributed Systems
Access conflicts in multiprocessor memories queueing models and simulation studies
ICS '90 Proceedings of the 4th international conference on Supercomputing
Reducing Interference Among Vector Accesses in Interleaved Memories
IEEE Transactions on Computers
Models of Access Delays in Multiprocessor Memories
IEEE Transactions on Parallel and Distributed Systems
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The data transfer capacity of a vector machine is a critical factor influencing the performance of the machine. The capacity is a function of several hardware and software parameters: the bandwidth of the crossing network between processing unit and memory, the number of independent memory modules, memory access configuration, types of vector operations, and the number of access ports in-use. Memory contention occurs in a multiple access port vector machine. When long vector operation performed, the machine efficiency is just the same as the efficiency of data transfer between memory and processing unit. A random bank choice model is proposed to analyze the memory contention and its influence on machine performance. The data obtained by the model are compared with the test results on the Cray X-MP and Y-MP, and the Ardent TITAN graphic minisupercomputers. The comparisons show that the modeling data and the test results match very well. One interesting conclusion from this model is that to preserve a constant level of memory access efficiency the number of independent memory banks should be proportional to the clocks of a memory active cycle as well as to the number of access ports.