Vector Computer Memory Bank Contention
IEEE Transactions on Computers
Some results in memory conflict analysis
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Memory conflicts and machine performance
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
The Operational Analysis of Queueing Network Models
ACM Computing Surveys (CSUR)
Measurement of memory access contentions in multiple vector processor systems
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Scalar Memory References in Pipelined Multiprocessors: A Performance Study
IEEE Transactions on Software Engineering
Characterizing memory performance in vector multiprocessors
ICS '92 Proceedings of the 6th international conference on Supercomputing
Synchronized access to streams in SIMD vector multiprocessors
ICS '94 Proceedings of the 8th international conference on Supercomputing
Compiling performance models from parallel programs
ICS '94 Proceedings of the 8th international conference on Supercomputing
A Memory Interference Model for Regularly Patterned Multiple Stream Vector Accesses
IEEE Transactions on Parallel and Distributed Systems
Vector multiprocessors with arbitrated memory access
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Models of Access Delays in Multiprocessor Memories
IEEE Transactions on Parallel and Distributed Systems
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The performance of an interleaved common memory accessed uniformly by multiple processors is modeled by queueing methods. The model includes access conflicts at the bank level while assuming an ideal access network.A scaling relation is derived that is generally valid and indicates that memory access delays are given by the product of the bank reservation time and a function of the memory utilization, which is given by the average number of access requests arriving at a bank per bank reservation time. For light memory traffic, access delays are proportional to the square of the bank reservation time and the ratio of the number of active memory access streams to the number of memory banks.Assuming random access patterns, an open and a closed queueing model are developed that are validated by simulations. Delay dependence on bank reservation time is quadratic for light loads and linear for very heavy loads.A heuristic extension of our model for vector accessing of banks in sequential mode is proposed.