Derivation of a Waiting-Time Factor for a Multiple-Bank Memory
Journal of the ACM (JACM)
A Combinatorial Problem Related to Interleaved Memory Systems
Journal of the ACM (JACM)
Anaysis of interleaved memory systems using blockage buffers
Communications of the ACM
On computing the fast Fourier transform
Communications of the ACM
Multi-processor software lockout
ACM '68 Proceedings of the 1968 23rd ACM national conference
Open, closed, and mixed networks of queues with different classes of customers.
Open, closed, and mixed networks of queues with different classes of customers.
An analysis of the instruction execution rate in certain computer structures
An analysis of the instruction execution rate in certain computer structures
Parallel programming: operational model and detection of parallelism
Parallel programming: operational model and detection of parallelism
Analysis of interleaved storage via a constant-service queuing system with Markov-chain-driven input
Journal of the ACM (JACM)
Exact performance estimates for multiprocessor memory and bus interference
IEEE Transactions on Computers
Vector Computer Memory Bank Contention
IEEE Transactions on Computers
Line (block) size choice for CPU cache memories
IEEE Transactions on Computers
Performance analysis of the FFT algorithm on a shared-memory parallel architecture
IBM Journal of Research and Development
Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
IEEE Transactions on Computers
Equilibrium Point Analysis of Memory Interference in Multiprocessor Systems
IEEE Transactions on Computers
Failure Dependent Bandwidth in Shuffle-Exchange Networks
IEEE Transactions on Computers
Performance Prediction and Calibration for a Class of Multiprocessors
IEEE Transactions on Computers
Analysis of bus hierarchies for multiprocessors
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Reducing memory contention in shared memory multiprocessors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Markovian Queueing Network Models for Performance Analysis of a Single-Bus Multiprocessor System
IEEE Transactions on Computers
Indirect Star-Type Networks for Large Multiprocessor Systems
IEEE Transactions on Computers
Performance Analysis of Multiple Bus Interconnection Networks with Hierarchical Requesting Model
IEEE Transactions on Computers
Design and Analysis of Master/Slave Multiprocessors
IEEE Transactions on Computers
Scalar Memory References in Pipelined Multiprocessors: A Performance Study
IEEE Transactions on Software Engineering
Factors in the performance of the AN1 computer network
SIGMETRICS '92/PERFORMANCE '92 Proceedings of the 1992 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Memory contention for shared memory vector multiprocessors
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
On Memory Contention Problems in Vector Multiprocessors
IEEE Transactions on Computers
IEEE/ACM Transactions on Networking (TON)
Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Functional Implementation Techniques for CPU Cache Memories
IEEE Transactions on Computers - Special issue on cache memory and related problems
Performance evaluation of interconnection networks in multiprocessor systems
ANSS '86 Proceedings of the 19th annual symposium on Simulation
The influence of parallel decomposition strategies on the performance of multiprocessor systems
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Analysis and simulation of multiplexed single-bus networks with and without buffering
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
A Survey of Parallel Machine Organization and Programming
ACM Computing Surveys (CSUR)
The impact of distributions and disciplines on multiple processor systems
Communications of the ACM
Multiprocessor memory organization and memory interference
Communications of the ACM
Models of Access Delays in Multiprocessor Memories
IEEE Transactions on Parallel and Distributed Systems
A performance evaluation of the multiple bus network for multiprocessor systems
SIGMETRICS '83 Proceedings of the 1983 ACM SIGMETRICS conference on Measurement and modeling of computer systems
An approximate analysis of multiprocessor systems
SIGMETRICS '83 Proceedings of the 1983 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Probabilistic analysis of a crossbar switch
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Analysis of multiprocessor cache organizations with alternative main memory update policies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Efficient interprocessor communication for MIMD multiprocessor systems
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Performance of memory configurations for parallel-pipelined computers
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Price/performance comparison of C.mmp and the PDP-10
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Reduction of memory interference in multiprocessor systems
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Simulation of multiprocessor computer with local memories
WSC '77 Proceedings of the 9th conference on Winter simulation - Volume 2
A simple model for cost considerations in a batch multiprocessor environment
ACM SIGMETRICS Performance Evaluation Review
Control functions for a multiprocessor architecture
ACM SIGOPS Operating Systems Review
Experiences with Performance Measurement and Modeling of a Processor Array
IEEE Transactions on Computers
Shared Cache for Multiple-Stream Computer Systems
IEEE Transactions on Computers
Modeling Bus Contention and Memory Interference in a Multiprocessor System
IEEE Transactions on Computers
Approximate Models of Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Markov Models for Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Analysis of Multiprocessors with Private Cache Memories
IEEE Transactions on Computers
Binary Search in a Multiprocessing Environment
IEEE Transactions on Computers
Performance of Cross-Bar Multiprocessor Systems
IEEE Transactions on Computers
Interference Analysis of Shuffle/Exchange Networks
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor
IEEE Transactions on Computers
Memory Interference in Synchronous Multiprocessor Systems
IEEE Transactions on Computers
A Closed-Form Solution for the Perfornance Analysis of Multiple-Bus Multiprocessor Systems
IEEE Transactions on Computers
Memory Interference Models with Variable Connection Time
IEEE Transactions on Computers
Comparative Performance Analysis of Single Bus Multiprocessor Architectures
IEEE Transactions on Computers
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors
IEEE Transactions on Computers
An analytic model for parallel computation
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Analysis of Delays Caused by Local Synchronization
SIAM Journal on Computing
Performance analysis of common bus multimicroprocessor systems
Journal of Systems and Software
On the product-form solution of a class of multiple-bus multiprocessor system models
Journal of Systems and Software
| Hi-index | 48.34 |
This paper analyzes the memory interference caused by several processors simultaneously using several memory modules. Exact results are computed for a simple model of such a system. The limiting value is derived for the relative degree of memory interference as the system size increases. The model of the limiting behavior of the system yields approximate results for the simple model and also suggests that the results are valid for a much larger class of models, including those more nearly like real systems than the simple model. The assumptions and results of the simple model are tested against some measurements of program behavior and simulations of systems using memory references from real programs. The model results provide a good indication of the performance that should be expected from real systems of this type.