Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
The design of the UNIX operating system
The design of the UNIX operating system
Sharp approximation models of adaptive routing in mesh networks (preliminary report)
Proc. of the international seminar on Teletraffic analysis and computer performance evaluation
Load-balancing heuristics and process behavior
SIGMETRICS '86/PERFORMANCE '86 Proceedings of the 1986 ACM SIGMETRICS joint international conference on Computer performance modelling, measurement and evaluation
Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
Simulation Techniques for Discrete Event Systems
Simulation Techniques for Discrete Event Systems
Fixed-Point Approximations for Distributed Systems
Proceedings of the International Workshop on Computer Performance and Reliability
Performance '87 Proceedings of the 12th IFIP WG 7.3 International Symposium on Computer Performance Modelling, Measurement and Evaluation
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
Z-iteration: a simple method for throughput estimation in time-dependent multi-class systems
Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Fast performance prediction of master-slave programs by partial task execution
SEPADS'05 Proceedings of the 4th WSEAS International Conference on Software Engineering, Parallel & Distributed Systems
| Hi-index | 14.98 |
A simple model of master/slave processors is presented, along with two simple, practical scheduling algorithms. An approximate analysis of the model yields simple formulas for performance measures in terms of the hardware and workload parameters, and gives insight into the power and the limitations of master/slave systems. In particular, formulae are obtained for the maximal processing power (throughput) of the system, a quantity that remains bounded as the number of slave processors increases. This analysis is applicable to symmetric multiprocessors, where performance considerations such as cache performance may dictate asymmetric assignment of system tasks to the processors.