Performance Analysis of Cache Memories
Journal of the ACM (JACM)
Concurrent Programming Concepts
ACM Computing Surveys (CSUR)
Multiprocessor memory organization and memory interference
Communications of the ACM
Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
Throughput analysis and configuration design of a shared-resource multiprocessor system: PUMPS
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Processor-memory interconnections for multiprocessors
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
The design and analysis of algorithms for asynchronous multiprocessors.
The design and analysis of algorithms for asynchronous multiprocessors.
Effects of cache coherency in multiprocessors
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Throughput analysis and configuration design of a shared-resource multiprocessor system: PUMPS
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Performance of cache-based multiprocessors
SIGMETRICS '81 Proceedings of the 1981 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Dynamic decentralized cache schemes for mimd parallel processors
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories
IEEE Transactions on Computers
PUMPS Architecture for Pattern Analysis and Image Database Management
IEEE Transactions on Computers
Effects of Cache Coherency in Multiprocessors
IEEE Transactions on Computers
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Several interprocessor communication mechanisms for multiprocessor systems have been proposed. An efficient communication scheme must facilitate high throughput and good response time. We introduce such an efficient scheme, describe the hardware involved, and evaluate its performance. The method is based on a compile-time tagging of shared data and on using different paths for “shared” (S-) and “private” (P-) data. The S-data accesses a shared cache on a word-by-word basis; the P-references are made to a local memory under a demand paging system. The resulting design avoids most shortcomings of other communication methods and supports multiprogrammed multiprocessor systems.