A simple linear model of demand paging performance
Communications of the ACM
Program Behavior: Models and Measurements
Program Behavior: Models and Measurements
Performance Evaluation of a Cache Memory for a Mini-computer
Proceedings of the Third International Symposium on Modelling and Performance Evaluation of Computer Systems: Performance of Computer Systems
Efficient interprocessor communication for MIMD multiprocessor systems
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Cache memories for PDP-11 family computers
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Performance of cache-based multiprocessors
SIGMETRICS '81 Proceedings of the 1981 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Computer
An Investigation of Alternative Cache Organizations
IEEE Transactions on Computers
A New Solution to Coherence Problems in Multicache Systems
IEEE Transactions on Computers
IEEE Transactions on Software Engineering
Cache system design in the tightly coupled multiprocessor system
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
A locking facility for parallel systems
IBM Systems Journal
Memory access buffering in multiprocessors
25 years of the international symposia on Computer architecture (selected papers)
Hardware Controlled Prefeching in Directory-Based Cache Coherent Systems
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories
IEEE Transactions on Computers
Synapse tightly coupled multiprocessors: a new approach to solve old problems
AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition
A new trace-driven shared-memory multiprocessors machine simulator
International Journal of Computers and Applications
| Hi-index | 14.98 |
In many commercial multiprocessor systems, each processor accesses the memory through a private cache. One problem that could limit the extensibility of the system and its performance is the enforcement of cache coherence. A mechanism must exist which prevents the existence of several different copies of the same data block in different private caches. In this paper, we present an in-depth analysis of the effects of cache coherency in multiprocessors. A novel analytical model for the program behavior of a multitasked system is introduced. The model includes the behavior of each process and the interactions between processes with regard to the sharing of data blocks. An approximation is developed to derive the main effects of the cache coherency contributing to degradations in system performance.