Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Correct memory operation of cache-based multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Efficient and correct execution of parallel programs that share memory
ACM Transactions on Programming Languages and Systems (TOPLAS)
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Effective Hardware-Based Data Prefetching for High-Performance Processors
IEEE Transactions on Computers
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
Effects of Cache Coherency in Multiprocessors
IEEE Transactions on Computers
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Sequential consistency is the popular accepted criterion of correct execution in shared-memory multi-processors. Typical implementation of sequential consistency requires each access to be delayed until the previous access in the same process completes. This is detrimental to performance. Perfechting is an effective way of overlapping the execution of memory accesses. This paper studies hardware-controlled perfechting in a directory-based cache coherent system, and proposes a new perfechting scheme as an improvement on the normal scheme. Besides, a cycle-by-cycle trace-driven simulation model is built to evaluate these perfechting schemes. Simulation results show that perfecting is effective in improving performance, and the new perfecting scheme we proposed can improve performance further.