Distributed discrete-event simulation
ACM Computing Surveys (CSUR)
Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Cache memory optimization to reduce processor/memory traffic
Advances in VLSI and Computer Systems
Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor
IEEE Transactions on Computers
Parallel simulation and its performance evaluation
Parallel simulation and its performance evaluation
The performance impact of flexibility in the Stanford FLASH multiprocessor
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Hive: fault containment for shared-memory multiprocessors
SOSP '95 Proceedings of the fifteenth ACM symposium on Operating systems principles
Using the SimOS machine simulator to study complex computer systems
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Trace-driven memory simulation: a survey
ACM Computing Surveys (CSUR)
Implementing a cache consistency protocol
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
IEEE Standard for Futurebust - Logical Protocol Specification: IEEE Std 896.1-1991
IEEE Standard for Futurebust - Logical Protocol Specification: IEEE Std 896.1-1991
The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions
The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions
Complete Computer System Simulation: The SimOS Approach
IEEE Parallel & Distributed Technology: Systems & Technology
A New Approach for the Verification of Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
Simulation analysis of data-sharing in shared memory multiprocessors
Simulation analysis of data-sharing in shared memory multiprocessors
Effects of Cache Coherency in Multiprocessors
IEEE Transactions on Computers
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As the gap between processor and memory speeds continues to widen, methods for measuring memory system designs before they are implemented in hardware are becoming increasingly important. The performance of the bus protocol maintaining the coherence of the same data in all caches for the shared-memory multiprocessors can be measured in advance by many analytical methods, the inevitable use of a simplified assumption to analyze a computer system with increasing complexity restrictions the predetermined conditions of the analytical results. The study introduces the development, implementation and future work for a trace-driven memory simulator for shared-memory multiprocessors. The simulator can measure the performance for different multiprocessors architectures under real operating systems and applications as a reference for the decision on the design or modification of the system, with the aim of increasing production efficiency and save R&D expenses.