Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
An Acyclic Expansion Algorithm for Fast Protocol Validation
IEEE Transactions on Software Engineering
The verification of cache coherence protocols
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
Symbolic state model: a new approach for the verification of cache coherence protocols
Symbolic state model: a new approach for the verification of cache coherence protocols
Proving circuit correctness using formal comparison between expected and extracted behaviour
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Verifying Concurrent Processes Using Temporal Logic
Verifying Concurrent Processes Using Temporal Logic
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Verification of Synchronous Sequential Machines Based on Symbolic Execution
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Verification of a Multiprocessor Cache Protocol Using Simulation Relations and Higher-Order Logic
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Exploiting Symmetry In Temporal Logic Model Checking
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Verification of the Futurebus+ Cache Coherence Protocol
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Dynamic decentralized cache schemes for mimd parallel processors
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Teapot: language support for writing memory coherence protocols
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
Verification techniques for cache coherence protocols
ACM Computing Surveys (CSUR)
Design Verification of the S3.mp Cache-Coherent Shared-Memory System
IEEE Transactions on Computers
Formal verification of complex coherence protocols using symbolic state models
Journal of the ACM (JACM)
Retrospective: memory access buffering in multiprocessors
25 years of the international symposia on Computer architecture (selected papers)
Verifying Systems with Replicated Components in Mur&b.phiv;
Formal Methods in System Design
Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models
IEEE Transactions on Parallel and Distributed Systems
A Design Phase Directed Formal Verification Process
Software Quality Control
Formal Verification of Delayed Consistency Protocols
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Verification Methods for Weaker Shared Memory Consistency Models
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Model Checking: Theory into Practice
FST TCS 2000 Proceedings of the 20th Conference on Foundations of Software Technology and Theoretical Computer Science
Proofs of Correctness of Cache-Coherence Protocols
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
Verifying Sequential Consistency on Shared-Memory Multiprocessor Systems
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Automated Inductive Verification of Parameterized Protocols
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Liveness with (0, 1, infty)-Counter Abstraction
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Verifying Sequential Consistency on Shared-Memory Multiprocessors by Model Checking
IEEE Transactions on Parallel and Distributed Systems
Constraint-Based Verification of Parameterized Cache Coherence Protocols
Formal Methods in System Design
Inductively Verifying Invariant Properties of Parameterized Systems
Automated Software Engineering
Automatic verification for a class of distributed systems
Distributed Computing
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Fair Model Checking with Process Counter Abstraction
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Efficient Reduction Techniques for Systems with Many Components
Electronic Notes in Theoretical Computer Science (ENTCS)
A new trace-driven shared-memory multiprocessors machine simulator
International Journal of Computers and Applications
Rapid parameterized model checking of snoopy cache coherence protocols
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Context-aware counter abstraction
Formal Methods in System Design
Fractal Coherence: Scalably Verifiable Cache Coherence
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
On combining state space reductions with global fairness assumptions
FM'11 Proceedings of the 17th international conference on Formal methods
Planning for end-to-end formal using simulation-based coverage: invited tutorial
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
SPIN'12 Proceedings of the 19th international conference on Model Checking Software
CSP-based counter abstraction for systems with node identifiers
Science of Computer Programming
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In this paper, we introduce a cache protocol verification technique based on a symbolic state expansion procedure. A global Finite State Machine (FSM) model characterizing the protocol behavior is built and protocol verification becomes equivalent to finding whether or not the global FSM may enter erroneous states. In order to reduce the complexity of the state expansion process, all the caches in the same state are grouped into an equivalence class and the number of caches in the class is symbolically represented by a repetition constructor. This symbolic representation is partly justified by the symmetry and homogeneity of cache-based systems. However, the key idea behind the representation is to exploit a unique property of cache coherence protocols: the fact that protocol correctness is not dependent on the exact number of cached copies. Rather, symbolic states only need to keep track of whether the caches have 0, 1, or multiple copies. The resulting symbolic state expansion process only takes a few steps and verifies the protocol for any system size. Therefore, it is more efficient and reliable than current approaches.The verification procedure is first applied to the verification of five existing protocols under the assumption of atomic protocol transitions. A simple snooping protocol on a split-transaction shared bus is also verified to illustrate the extension of our approach to protocols with nonatomic transitions.