Invariance and non-determinacy
Proc. of a discussion meeting of the Royal Society of London on Mathematical logic and programming languages
Limits for automatic verification of finite-state concurrent systems
Information Processing Letters
Avoiding the state explosion problem in temporal logic model checking
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
A structural induction theorem for processes
Proceedings of the eighth annual ACM Symposium on Principles of distributed computing
Verifying properties of large sets of processes with network invariants
Proceedings of the international workshop on Automatic verification methods for finite state systems
Reasoning about systems with many processes
Journal of the ACM (JACM)
Formal specification of abstract memory models
Proceedings of the 1993 symposium on Research on integrated systems
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
Property preserving abstractions for the verification of concurrent systems
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
A structural linearization principle for processes
Formal Methods in System Design
An executable specification, analyzer and verifier for RMO (relaxed memory order)
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
System design methodology of ultraSPARC-I
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Teapot: language support for writing memory coherence protocols
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Symbolic state model: a new approach for the verification of cache coherence protocols
Symbolic state model: a new approach for the verification of cache coherence protocols
State reduction using reversible rules
DAC '96 Proceedings of the 33rd annual Design Automation Conference
State reduction methods for automatic formal verification
State reduction methods for automatic formal verification
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
A New Approach for the Verification of Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study
Euro-Par '95 Proceedings of the First International Euro-Par Conference on Parallel Processing
Automatic verification of the SCI cache coherence protocol
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Veryfying Parameterized Networks using Abstraction and Regular Languages
CONCUR '95 Proceedings of the 6th International Conference on Concurrency Theory
Automatic Generation of Network Invariants for the Verification of Iterative Sequential Systems
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
A Tool for Symbolic Program Verification and Abstration
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Verification of a Distributed Cache Memory by Using Abstractions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
On the Automatic Computation of Network Invariants
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Computer-assisted analysis of multiprocessor memory systems
Computer-assisted analysis of multiprocessor memory systems
Model checking systems of replicated processes with spin
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
On the Existence of Network Invariants for Verifying Parameterized Systems
Correct System Design, Recent Insight and Advances, (to Hans Langmaack on the occasion of his retirement from his professorship at the University of Kiel)
Verification of Parameterized Systems Using Logic Program Transformations
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Automated Inductive Verification of Parameterized Protocols
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Constraint-Based Verification of Parameterized Cache Coherence Protocols
Formal Methods in System Design
Inductively Verifying Invariant Properties of Parameterized Systems
Automated Software Engineering
Live and let die: LSC based verification of UML models
Science of Computer Programming - Formal methods for components and objects pragmatic aspects and applications
Compositional analysis for verification of parameterized systems
Theoretical Computer Science - Tools and algorithms for the construction and analysis of systems (TACAS 2003)
Feature interaction detection by pairwise analysis of LTL properties: a case study
Formal Methods in System Design
Computer Networks: The International Journal of Computer and Telecommunications Networking
An automatic abstraction technique for verifying featured, parameterised systems
Theoretical Computer Science
Fair Model Checking with Process Counter Abstraction
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Efficient Reduction Techniques for Systems with Many Components
Electronic Notes in Theoretical Computer Science (ENTCS)
Compositional analysis for verification of parameterized systems
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Verifying parameterized taDOM+ lock managers
SOFSEM'08 Proceedings of the 34th conference on Current trends in theory and practice of computer science
An invariant-based approach to the verification of asynchronous parameterized networks
Journal of Symbolic Computation
Reducing model checking of the few to the one
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Model-Checking parameterized concurrent programs using linear interfaces
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Parameterized verification of π-calculus systems
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Proceedings of the 41st ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages
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An extension to the Mur&b.phiv; verifier is presented to verifysystems with replicated identical components. Although most systems are finite-statein nature, many of them are also designed to be scalable, so that adescription gives a family of systems, each member of which has adifferent number of replicated components. It is thereforedesirable to be able to verify the entire family of systems,independent of the exact number of replicated components.The verification is performed by explicit state enumeration in anabstract state space where states do not record the exact numbers ofcomponents. We provide an extension to the existing Mur&b.phiv; language, bywhich a designer can easily specify a system in its concrete form.Through a new datatype, called RepetitiveID, a designer can suggest the use of this abstraction to verify a family of systems.First of all, Mur&b.phiv; automatically checks the soundness of thisabstraction. Then it automatically translates the systemdescription to an abstract state graph for a system of a fixed size.During the verification of the system of a fixed size, Mur&b.phiv; uses asimple run-time check to determine if the result can be generalized for afamily of systems with sizes larger than the original system, including the system with an unbounded number ofcomponents.