Limits for automatic verification of finite-state concurrent systems
Information Processing Letters
Characterizing finite Kripke structures in propositional temporal logic
Theoretical Computer Science - International Joint Conference on Theory and Practice of Software Development, P
A structural induction theorem for processes
Proceedings of the eighth annual ACM Symposium on Principles of distributed computing
Model checking and abstraction
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Reasoning about systems with many processes
Journal of the ACM (JACM)
POPL '95 Proceedings of the 22nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Formal Methods in System Design - Special issue on symmetry in automatic verification
Verifying parameterized networks
ACM Transactions on Programming Languages and Systems (TOPLAS)
IFIP TC6/ 6.1 international conference on formal description techniques IX/protocol specification, testing and verification XVI on Formal description techniques IX : theory, application and tools: theory, application and tools
Verifying Systems with Replicated Components in Mur&b.phiv;
Formal Methods in System Design
Verification by augmented finitary abstraction
Information and Computation
Testing Computer Software, Second Edition
Testing Computer Software, Second Edition
Verifying End-to-End Protocols using Induction with CSP/FDR
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
Fair Simulation Relations, Parity Games, and State Space Reduction for Büchi Automata
ICALP '01 Proceedings of the 28th International Colloquium on Automata, Languages and Programming,
Industrial Applications of Model Checking
MOVEP '00 Proceedings of the 4th Summer School on Modeling and Verification of Parallel Processes
Network Grammars, Communication Behaviors and Automatic Verification
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Verifying Properties of Large Sets of Processes with Network Invariants
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Veryfying Parameterized Networks using Abstraction and Regular Languages
CONCUR '95 Proceedings of the 6th International Conference on Concurrency Theory
A Heuristic for Symmetry Reductions with Scalarsets
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
Structural Symmetry and Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Exploiting Symmetry In Temporal Logic Model Checking
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Automatic Abstraction Techniques for Propositional µ-calculus Model Checking
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Verification of the Futurebus+ Cache Coherence Protocol
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
Software verification with BLAST
SPIN'03 Proceedings of the 10th international conference on Model checking software
Automatic symmetry detection for model checking using computational group theory
FM'05 Proceedings of the 2005 international conference on Formal Methods
Game-theoretic simulation checking tool
Programming and Computing Software
The Journal of Supercomputing
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A uniform verification problem for parameterized systems is to determine whether a temporal property is satisfied for every instance of the system which is composed of an arbitrary number of homogeneous processes. To cope with this problem we combine an induction-based technique for invariant generation and conventional model checking of finite state systems. At the first stage of verification we try to select automatically an appropriate invariant system. At the second stage, as soon as an invariant of the parameterized system is obtained, we verify it by means of a conventional model checking tool for temporal logics. An invariant system is one that is greater (with respect to some preorder relation) than any instance of the parameterized system. Therefore, the preorder relation involved in the invariant rule is of considerable importance. For this purpose we introduce a new type of simulation preorder - quasi-block simulation. We show that quasi-block simulation preserves the satisfiability of formulae from ACTL^@?-X and that asynchronous composition of processes is monotonic w.r.t. quasi-block simulation. This suggests the use of quasi-block simulation in the induction-based verification techniques for asynchronous networks. To demonstrate the feasibility of quasi-block simulation we implemented this technique and applied it to the verification of the Resource ReSerVation Protocol (RSVP).