Design and validation of computer protocols
Design and validation of computer protocols
Stubborn sets for reduced state generation
APN 90 Proceedings on Advances in Petri nets 1990
Handbook of theoretical computer science (vol. B)
Memory-efficient algorithms for the verification of temporal properties
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Exploiting symmetry in temporal logic model checking
Formal Methods in System Design - Special issue on symmetry in automatic verification
Utilizing symmetry when model-checking under fairness assumptions: an automata-theoretic approach
ACM Transactions on Programming Languages and Systems (TOPLAS)
State reduction methods for automatic formal verification
State reduction methods for automatic formal verification
Distributed Algorithms
Model Checking Real-Time Properties of Symmetric Systems
MFCS '98 Proceedings of the 23rd International Symposium on Mathematical Foundations of Computer Science
Integrating Real Time into Spin: A Prototype Implementation
FORTE XI / PSTV XVIII '98 Proceedings of the FIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XI) and Protocol Specification, Testing and Verification (PSTV XVIII)
Exploiting Symmetry when Model-Checking Software
FORTE XII / PSTV XIX '99 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XII) and Protocol Specification, Testing and Verification (PSTV XIX)
Combining Partial Order and Symmetry Reductions
TACAS '97 Proceedings of the Third International Workshop on Tools and Algorithms for Construction and Analysis of Systems
From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
On-the-Fly Model Checking Under Fairness That Exploits Symmetry
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Proceedings of the 7th International SPIN Workshop on SPIN Model Checking and Software Verification
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Symmetry Reduction Criteria for Software Model Checking
Proceedings of the 9th International SPIN Workshop on Model Checking of Software
Exploiting Heap Symmetries in Explicit-State Model Checking of Software
Proceedings of the 16th IEEE international conference on Automated software engineering
An invariant-based approach to the verification of asynchronous parameterized networks
Journal of Symbolic Computation
Symbolic model checking of finite precision timed automata
ICTAC'05 Proceedings of the Second international conference on Theoretical Aspects of Computing
State space c-reductions of concurrent systems in rewriting logic
ICFEM'12 Proceedings of the 14th international conference on Formal Engineering Methods: formal methods and software engineering
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We present four versions of a new heuristic for coping with the problem of finding (canonical) representatives of symmetry equivalence classes (the so-called orbit problem), in symmetry techniques for model checking. The practical implementation of such techniques hinges on appropriate workarounds of this hard problem, which is equivalent to graph isomorphism. We implemented the four strategies on top of the Spin model checker, and compared their performance on several examples, with encouraging results.