Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Fairness
Modalities for model checking: branching time logic strikes back
Science of Computer Programming
Reasoning about networks with many identical finite state processes
Information and Computation
High-level Petri nets: theory and application
High-level Petri nets: theory and application
Online minimization of transition systems (extended abstract)
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
Minimal state graph generation
Science of Computer Programming
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Coloured Petri nets: basic concepts, analysis methods and practical use, vol. 2
Coloured Petri nets: basic concepts, analysis methods and practical use, vol. 2
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Formal Methods in System Design - Special issue on symmetry in automatic verification
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Analysing Concurrent Systems Using the Concurrency Workbench
Functional Programming, Concurrency, Simulation and Automated Reasoning: International Lecture Series 1991-1992, McMaster University, Hamilton, Ontario, Canada
Exploiting Symmetry In Temporal Logic Model Checking
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Generation of Reduced Models for Checking Fragments of CTL
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Automata theoretic techniques for modal logics of programs: (Extended abstract)
STOC '84 Proceedings of the sixteenth annual ACM symposium on Theory of computing
Automated formal methods: model checking and beyond
ACM SIGSOFT Software Engineering Notes
Efficient and User-Friendly Verification
IEEE Transactions on Computers
Designing reactive systems: integration of abstraction techniques into a synthesis procedure
Journal of Systems and Software - Special issue on artificial and computational intelligence for decisions, control, and automation in engineering and industrial applications
Region Encoding Diagram for Fully Symbolic Verification of Real-Time Systems
COMPSAC '00 24th International Computer Software and Applications Conference
Symmetric Symbolic Safety-Analysis of Concurrent Software with Pointer Data Structures
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
A Nested Depth First Search Algorithm for Model Checking with Symmetry Reduction
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Model Checking Large-Scale and Parameterized Resource Allocation Systems
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Model Checking: Theory into Practice
FST TCS 2000 Proceedings of the 20th Conference on Foundations of Software Technology and Theoretical Computer Science
Analysis and Verification Queries over Object-Oriented Petri Nets
Computer Aided Systems Theory - EUROCAST 2001-Revised Papers
A Heuristic for Symmetry Reductions with Scalarsets
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
Parameterized Verification with Automatically Computed Inductive Assertions
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Automatic Verification of Pointer Data-Structure Systems for All Numbers of Processes
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume I - Volume I
LICS '00 Proceedings of the 15th Annual IEEE Symposium on Logic in Computer Science
IEEE Transactions on Software Engineering
Symmetry and reduced symmetry in model checking
ACM Transactions on Programming Languages and Systems (TOPLAS)
Symmetry in temporal logic model checking
ACM Computing Surveys (CSUR)
Combining symmetry reduction and under-approximation for symbolic model checking
Formal Methods in System Design
Journal of Embedded Computing - Real-Time and Embedded Computing Systems
Verification of parametric concurrent systems with prioritised FIFO resource management
Formal Methods in System Design
The Beginning of Model Checking: A Personal Perspective
25 Years of Model Checking
Control of Parameterized Discrete Event Systems
Discrete Event Dynamic Systems
Fair Model Checking with Process Counter Abstraction
FM '09 Proceedings of the 2nd World Congress on Formal Methods
On combining state space reductions with global fairness assumptions
FM'11 Proceedings of the 17th international conference on Formal methods
Verification of orchestration systems using compositional partial order reduction
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
Environment abstraction for parameterized verification
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Symmetry reduction in SAT-based model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Symmetry reduction for probabilistic model checking using generic representatives
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Concurrency, Compositionality, and Correctness
A complete method for symmetry reduction in safety verification
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Finding Symmetries of Algebraic System Nets
Fundamenta Informaticae
Hi-index | 0.00 |
One useful technique for combating the state explosion problem is to exploit symmetry when performing temporal logic model checking. In previous work it is shown how, using some basic notions of group theory, symmetry may be exploited for the full range of correctness properties expressible in the very expressive temporal logic CTL*. Surprisingly, while fairness properties are readily expressible in CTL*, these methods are not powerful enough to admit any amelioration of state explosion, when fairness assumptions are involved. We show that it is nonetheless possible to handle fairness efficiently by trading some group theory for automata theory. Our automata-theoretic approach depends on detecting fair paths subtly encoded in a quotient structure whose arcs are annotated with permutations, by using a threaded structure that reflects coordinate shifts caused by the permutations.