Communicating sequential processes
Communicating sequential processes
A fast mutual exclusion algorithm
ACM Transactions on Computer Systems (TOCS)
Computer networks
Communication and concurrency
Design and validation of computer protocols
Design and validation of computer protocols
Compiling Real-Time Specifications into Extended Automata
IEEE Transactions on Software Engineering - Special issue: specification and analysis of real-time systems
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Fischer's protocol revisited: a simple proof using modal constraints
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Utilizing symmetry when model-checking under fairness assumptions: an automata-theoretic approach
ACM Transactions on Programming Languages and Systems (TOPLAS)
Symbolic Model Checking
Automatic Verification on the Large
HASE '98 The 3rd IEEE International Symposium on High-Assurance Systems Engineering
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
FORTE XII / PSTV XIX '99 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XII) and Protocol Specification, Testing and Verification (PSTV XIX)
Compositional Model Checking of Real Time Systems
CONCUR '95 Proceedings of the 6th International Conference on Concurrency Theory
"On the Fly" Verification of Behavioural Equivalences and Preorders
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
Refining Dependencies Improves Partial-Order Verification Methods (Extended Abstract)
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Analysis of Timed Systems Based on Time-Abstracting Bisimulation
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Saving Space by Fully Exploiting Invisible Transitions
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
An Old-Fashioned Recipe for Real Time
Proceedings of the Real-Time: Theory in Practice, REX Workshop
A State Graph Manipulator Tool for Real-Time System Specification and Verification
RTCSA '98 Proceedings of the 5th International Conference on Real-Time Computing Systems and Applications
Compositional and symbolic model-checking of real-time systems
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Approximate reachability analysis of timed automata
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Reducing the number of clock variables of timed automata
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Efficient verification of real-time systems: compact data structure and state-space reduction
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Symmetric Symbolic Safety-Analysis of Concurrent Software with Pointer Data Structures
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Improving the Verification of Timed Systems Using Influence Information
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Efficient Verification of Timed Automata with BDD-Like Data-Structures
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
IEEE Transactions on Software Engineering
VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software
IEEE Transactions on Software Engineering
Journal of Embedded Computing - Real-Time and Embedded Computing Systems
TCTL Inevitability Analysis of Dense-Time Systems: From Theory to Engineering
IEEE Transactions on Software Engineering
Model Checking Safety-Critical Systems Using Safecharts
IEEE Transactions on Computers
Computer Languages, Systems and Structures
Modeling and verification of real-time embedded systems with urgency
Journal of Systems and Software
VERTAF/Multi-Core: A SysML-Based Application Framework for Multi-Core Embedded Software Development
ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
Real-Time Embedded Software Design for Mobile and Ubiquitous Systems
Journal of Signal Processing Systems
TCTL inevitability analysis of dense-time systems
CIAA'03 Proceedings of the 8th international conference on Implementation and application of automata
Real-time embedded software design for mobile and ubiquitous systems
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Symbolic verification of distributed real-time systems with complex synchronizations
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
Model checking prioritized timed automata
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Interoperability of constrained finite state automata
ACM SIGSOFT Software Engineering Notes
Modeling and verification of safety-critical systems using safecharts
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Model checking timed systems with urgencies
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Modeling and automatic failure analysis of safety-critical systems using extended safecharts
SAFECOMP'07 Proceedings of the 26th international conference on Computer Safety, Reliability, and Security
Efficient model-checking of dense-time systems with time-convexity analysis
Theoretical Computer Science
| Hi-index | 14.99 |
A compositional verification method from a high-level resource-management standpoint is presented for dense-time concurrent systems and implemented in the tool of SGM (State-Graph Manipulators) with graphical user interface. SGM packages sophisticated verification technology into state-graph manipulators and provides a user interface which views state-graphs as basic data-objects. Hence, users do not have to be verification theory experts and do not have to trace inside state-graphs to analyze state and path properties to make the best use of verification theory. Instead, users can construct their own verification strategies based on observation on the state-graph complexity changes after experimenting with some combinations of manipulators. Moreover, SGM allows users to control the complexity of state-graphs through iterative state-graphs merging and reductions before they become out of control. Reduction techniques specially designed for the context of state-graph iteration composition and shared variable manipulations are developed and used in SGM. Experiments on different benchmarks to show SGM performance are reported. An algorithm based on group theory to pick a manipulator combination is presented.