Theoretical Computer Science
Safeware: system safety and computers
Safeware: system safety and computers
Model checking
Efficient and User-Friendly Verification
IEEE Transactions on Computers
Scheduler Modeling Based on the Controller Synthesis Paradigm
Real-Time Systems
Model Checking Safety Properties of Servo-Loop Control Systems
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
A State Graph Manipulator Tool for Real-Time System Specification and Verification
RTCSA '98 Proceedings of the 5th International Conference on Real-Time Computing Systems and Applications
Safecharts for Specifying and Designing Safety Critical Systems
SRDS '99 Proceedings of the 18th IEEE Symposium on Reliable Distributed Systems
Risk Bands - A Novel Feature of Safecharts
ISSRE '00 Proceedings of the 11th International Symposium on Software Reliability Engineering
Model Checking Safety-Critical Systems Using Safecharts
IEEE Transactions on Computers
Model checking prioritized timed automata
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Model checking timed systems with urgencies
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
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With the rapid progress in science and technology, we find ubiquitous use of safety-critical systems in avionics, consumer electronics, and medical instruments. In such systems, unintentional design faults might result in injury or even death to human beings. To avoid such mishaps, we need to verify safety-critical systems thoroughly, where formal verification techniques such as model checking play a very promising role. Currently, there is practically no automatic technique in formal verification used to formally model system faults and repairs. This work contributes in proposing an extension to the Safecharts model, with which faults and repairs can be easily modeled. Moreover, these Safecharts can be directly transformed into semantically equivalent Extended Timed Automata models for model checking. That is, after these models were integrated into a model checker, such as our previously proposed State Graph Manipulators (SGM) model checker, we can verify safety-critical systems. An application example is run to show the feasibility and benefits of the proposed model-driven verification method for safety-critical systems. As observed, the checking results, such as witnesses of property specifications representing hazards, provide more concrete and useful failure analysis information than the conventional Fault Tree Analysis (FTA).