Model checking prioritized timed automata

  • Authors:

  • Shang-Wei Lin;Pao-Ann Hsiung;Chun-Hsian Huang;Yean-Ru Chen

  • Affiliations:

  • Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC

  • Venue:
  • ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
  • Year:
  • 2005

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Abstract

Priorities are often used to resolve conflicts in timed systems. However, priorities are not directly supported by state-of-art model checkers. Often, a designer has to either abstract the priorities leading to a high degree of non-determinism or model the priorities using existing primitives. In this work, it is shown how prioritized timed automata can make modelling prioritized timed systems easier through the support for priority specification and model checking. The verification of prioritized timed automata requires a subtraction operation to be performed on two clock zones, represented by DBMs, for which we propose an algorithm to generate the minimal number of zones partitioned. After the application of a series of DBM subtraction operations, the number of zones generated become large. We thus propose an algorithm to reduce the final number of zones partitioned by merging some of them. A typical bus arbitration example is used to illustrate the benefits of the proposed algorithms. Due to the support for prioritization and zone reduction, we observe that there is a 50% reduction in the number of modes and 44% reduction in the number of transitions.