Model checking timed systems with urgencies

Authors:
Pao-Ann Hsiung;Shang-Wei Lin;Yean-Ru Chen;Chun-Hsian Huang;Jia-Jen Yeh;Hong-Yu Sun;Chao-Sheng Lin;Hsiao-Win Liao
Affiliations:
Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC
Venue:
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Year:
2006

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Abstract

Computation tree logic (CTL) model checkers either allow modeling of only lazy semantics in the timed system model or consider at most a simple as soon as possible semantics. However, the design of real-time systems requires different types of urgencies, which have been modeled by several urgency variants of the timed automata model. Except for the IF toolset that model checks timed automata with urgency against observers, the urgency variants of timed automata have not yet been used for verifying the satisfaction of CTL properties in real-time systems. This work is targeted at proposing a zone-based urgency semantics that is time-reactive and at model checking timed automata models that have been extended with such urgency semantics for delayable and eager transition types. Interactions among these different types of transition urgencies are also investigated. The proposed verification methods were implemented in the SGM CTL model checker and applied to real-time and embedded systems. Several experiments, comparing the state space sizes produced by SGM with that by the IF toolset, show that SGM produces much smaller state-spaces.