Communicating sequential processes
Communicating sequential processes
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Introduction to the ISO specification language LOTOS
Computer Networks and ISDN Systems - Special Issue: Protocol Specification and Testing
Design and validation of computer protocols
Design and validation of computer protocols
Model-checking in dense real-time
Information and Computation - Special issue: selections from 1990 IEEE symposium on logic in computer science
Symbolic model checking for real-time systems
Information and Computation
An introduction to ET-LOTOS for the description of time-sensitive systems
Computer Networks and ISDN Systems
An experiment in automatic generation of test suites for protocols with verification technology
Science of Computer Programming - Special issue on COST 247, verification and validation methods for formal descriptions
Science of Computer Programming - Special issue on COST 247, verification and validation methods for formal descriptions
An improved algorithm for decentralized extrema-finding in circular configurations of processes
Communications of the ACM
Systems Engineering Using SDL-92
Systems Engineering Using SDL-92
Compilation and verification of LOTOS specifications
Proceedings of the IFIP WG6.1 Tenth International Symposium on Protocol Specification, Testing and Verification X
Integrating Real Time into Spin: A Prototype Implementation
FORTE XI / PSTV XVIII '98 Proceedings of the FIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XI) and Protocol Specification, Testing and Verification (PSTV XVIII)
Compositional State Space Generation from Lotos Programs
TACAS '97 Proceedings of the Third International Workshop on Tools and Algorithms for Construction and Analysis of Systems
OPEN/CÆSAR: An OPen Software Architecture for Verification, Simulation, and Testing
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Extending Promela and Spin for Real Time
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Modeling Urgency in Timed Systems
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
State Space Reduction Based on Live Variables Analysis
SAS '99 Proceedings of the 6th International Symposium on Static Analysis
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Compositionality in State Space Verification Methods
Proceedings of the 17th International Conference on Application and Theory of Petri Nets
Computing Abstractions of Infinite State Systems Compositionally and Automatically
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
CADP - A Protocol Validation and Verification Toolbox
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Discrete time process algebra and the semantics of SDL
Discrete time process algebra and the semantics of SDL
Verification experiments on the MASCARA protocol
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
Composable semantics for model-based notations
ACM SIGSOFT Software Engineering Notes
NTIF: A General Symbolic Model for Communicating Sequential Processes with Data
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Mechanization of an Integrated Approach: Shallow Embedding into SAL/PVS
ICFEM '02 Proceedings of the 4th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Synchronous Closing of Timed SDL Systems for Model Checking
VMCAI '02 Revised Papers from the Third International Workshop on Verification, Model Checking, and Abstract Interpretation
Automated Test and Oracle Generation for Smart-Card Applications
E-SMART '01 Proceedings of the International Conference on Research in Smart Cards: Smart Card Programming and Security
Closing Open SDL-Systems for Model Checking with DTSpin
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
Basic-REAL: Integrated Approach for Design, Specification and Verification of Distributed Systems
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
Basic protocols, message sequence charts, and the verification of requirements specifications
Computer Networks: The International Journal of Computer and Telecommunications Networking - Telecommunications and UML languages
Actor-based slicing techniques for efficient reduction of Rebeca models
Science of Computer Programming
A dynamic assertion-based verification platform for validation of UML designs
ACM SIGSOFT Software Engineering Notes
Model checking timed systems with urgencies
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Fundamenta Informaticae - Fundamentals of Software Engineering 2007: Selected Contributions
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Formal Description Techniques (FDT), such as lotos or sdl are at the base of a technology for the specification and the validation of telecommunication systems. Due to the availability of commercial tools, these formalisms are now being widely used in the industrial community. Alternatively, a number of quite efficient verification tools have been developed by the research community. But, most of these tools are based on simple ad hoc formalisms and the gap between them and real FDT restricts their use at industrial scale. This context motivated the development of an intermediate representation called IF which is presented in the paper. IF has a simple syntactic structure, but allows to express in a convenient way most useful concepts needed for the specification of timed asynchronous systems. The benefits of using IF are multiples. First, it is general enough to handle significant subsets of most FDTs, and in particular a translation from SDL to IF is already implemented. Being built upon a mathematically sound model (extended timed automata) it allows to properly evaluate different semantics for fdts, in particular with respect to time considerations. Finally, IF can serve as a basis for interconnecting various tools into a unified validation framework. Several levels of IF program representations are already available via well defined APIs and allow to connect tools ranging from static analyzers to model-checkers.