Current trends in concurrency. Overviews and tutorials
Automatic verification of finite state machines using temporal logic
Automatic verification of finite state machines using temporal logic
An action-based framework for verifying logical and behavioural properties of concurrent systems
Computer Networks and ISDN Systems - Special issue on tools for FDTs
Real-time object-oriented modeling
Real-time object-oriented modeling
Three logics for branching bisimulation
Journal of the ACM (JACM)
LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
Enriching OCL Using Observational Mu-Calculus
FASE '02 Proceedings of the 5th International Conference on Fundamental Approaches to Software Engineering
Modal Transition Systems: A Foundation for Three-Valued Program Analysis
ESOP '01 Proceedings of the 10th European Symposium on Programming Languages and Systems
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
IF: An Intermediate Representation and Validation Environment for Timed Asynchronous Systems
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume I - Volume I
ESTL: A Temporal Logic for Events and States
ICATPN '98 Proceedings of the 19th International Conference on Application and Theory of Petri Nets
Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
An OCL Extension for Real-Time Constraints
Object Modeling with the OCL, The Rationale behind the Object Constraint Language
vUML: A Tool for Verifying UML Models
ASE '99 Proceedings of the 14th IEEE international conference on Automated software engineering
Model Checking for an Executable Subset of UML
Proceedings of the 16th IEEE international conference on Automated software engineering
Towards the compositional verification of real-time UML designs
Proceedings of the 9th European software engineering conference held jointly with 11th ACM SIGSOFT international symposium on Foundations of software engineering
Fluent model checking for event-based systems
Proceedings of the 9th European software engineering conference held jointly with 11th ACM SIGSOFT international symposium on Foundations of software engineering
Event-based runtime verification of java programs
WODA '05 Proceedings of the third international workshop on Dynamic analysis
A Roadmap for Formal Property Verification
A Roadmap for Formal Property Verification
Mop: an efficient and generic runtime verification framework
Proceedings of the 22nd annual ACM SIGPLAN conference on Object-oriented programming systems and applications
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
A Dynamic Assertion-Based Verification Platform for Validation of UML Designs
ATVA '08 Proceedings of the 6th International Symposium on Automated Technology for Verification and Analysis
Temporal Assertions using AspectJ
Electronic Notes in Theoretical Computer Science (ENTCS)
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Capacity limitations continue to impede widespread adoption of formal property verification in the design validation ow of software and hardware systems. The more popular choice (at least in the hardware domain) has been dynamic property verification (DPV), which is a semi-formal approach where the formal properties are checked over simulation runs. DPV is highly scalable and can support a rich specification language. The main contribution of this paper is to build an integrated DPV platform for validation of UML-based designs. Specifically, we present (a) a language, named Action-LTL (a simple extension of Linear Temporal Logic) for writing assertions over data attributes and events of UML models, and (b) an integrated dynamic assertion-verification platform for verification of UML designs. In view of the capacity limitations of existing formal property verification tools, we believe that the methods presented in this paper are of immediate practical value to the UML design community.