Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
On-the-fly verification of finite transition systems
Formal Methods in System Design - Special issue on computer-aided verification: general methods
An experiment in automatic generation of test suites for protocols with verification technology
Science of Computer Programming - Special issue on COST 247, verification and validation methods for formal descriptions
Automatically closing open reactive programs
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Advanced compiler design and implementation
Advanced compiler design and implementation
Verification and test generation for the SSCOP protocol
Science of Computer Programming
Symbolic Model Checking
Partial-Order Methods for the Verification of Concurrent Systems: An Approach to the State-Explosion Problem
POPL '83 Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Static Partial Order Reduction
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
On-the-Fly Analysis of Systems with Unbounded, Lossy FIFO Channels
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Computing Abstractions of Infinite State Systems Compositionally and Automatically
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
CADP - A Protocol Validation and Verification Toolbox
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Reducing the number of clock variables of timed automata
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Verifying Large SDL-Specifications Using Model Checking
SDL '01 Proceedings of the 10th International SDL Forum Copenhagen on Meeting UML
Closing Open SDL-Systems for Model Checking with DTSpin
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
IF: An Intermediate Representation and Validation Environment for Timed Asynchronous Systems
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume I - Volume I
Compressing Transitions for Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
State Space Reduction of Linear Processes Using Control Flow Reconstruction
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
Application of static analyses for state-space reduction to the microcontroller binary code
Science of Computer Programming
Reducing quasi-equal clocks in networks of timed automata
FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
Abstract interpretation of microcontroller code: Intervals meet congruences
Science of Computer Programming
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The intrinsic complexity of most protocol specifications in particular, and of asynchronous systems in general, lead us to study combinations of static analysis with classical model-checking techniques as a way to enhance the performances of automated validation tools. The goal of this paper is to point out that an equivalence on our model derived from the information on live variables is stronger than the strong bisimulation. This equivalence, further called live bisimulation, exploits the unused dead values stored either in variables or in queue contents and allow to simplify the state space with a rather important factor. Furthermore, this reduction comes almost for free and is always possible to directly generate the quotient model without generating the initial one.