Theoretical Computer Science
Wireless Communications: Principles and Practice
Wireless Communications: Principles and Practice
Model Checking of Real-Time Reachability Properties Using Abstractions
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Improving the Verification of Timed Systems Using Influence Information
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
State Space Reduction Based on Live Variables Analysis
SAS '99 Proceedings of the 6th International Symposium on Static Analysis
Reducing the number of clock variables of timed automata
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Real-Time Systems: Formal Specification and Automatic Verification
Real-Time Systems: Formal Specification and Automatic Verification
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Disambiguation of industrial standards through formalization and graphical languages
RE '11 Proceedings of the 2011 IEEE 19th International Requirements Engineering Conference
Timed automata with disjoint activity
FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
Timed automata with disjoint activity
FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
Detecting quasi-equal clocks in timed automata
FORMATS'13 Proceedings of the 11th international conference on Formal Modeling and Analysis of Timed Systems
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We introduce the novel notion of quasi-equal clocks and use it to improve the verification time of networks of timed automata. Intuitively, two clocks are quasi-equal if, during each run of the system, they have the same valuation except for those points in time where they are reset. We propose a transformation that takes a network of timed automata and yields a network of timed automata which has a smaller set of clocks and preserves properties up to those not comparing quasi-equal clocks. Our experiments demonstrate that the verification time in three transformed real world examples is much lower compared to the original.