Computer Communications - Special issue on practical use of FDTs in communications & distributed systems
Theoretical Computer Science
UPPAAL—a tool suite for automatic verification of real-time systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
An algebraic framework for urgency
Information and Computation
Efficient and User-Friendly Verification
IEEE Transactions on Computers
Compositional Specification of Timed Systems (Extended Abstract)
STACS '96 Proceedings of the 13th Annual Symposium on Theoretical Aspects of Computer Science
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
A State Graph Manipulator Tool for Real-Time System Specification and Verification
RTCSA '98 Proceedings of the 5th International Conference on Real-Time Computing Systems and Applications
Timed I/O Automata: A Mathematical Framework for Modeling and Analyzing Real-Time Systems
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Timed automata with urgent transitions
Acta Informatica
Specifying Urgency in Timed I/O Automata
SEFM '05 Proceedings of the Third IEEE International Conference on Software Engineering and Formal Methods
Model checking prioritized timed automata
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Journal of Systems Architecture: the EUROMICRO Journal
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Real-time embedded systems are often designed with different types of urgencies such as delayable or eager, that are modeled by several urgency variants of the timed automata model. However, most model checkers do not support such urgency semantics, except for the IF toolset that model checks timed automata with urgency against observers. This work proposes an Urgent Timed Automata (UTA) model with zone-based urgency semantics that gives the same model checking results as absolute urgency semantics of other existing urgency variants of the timed automata model, including timed automata with deadlines and timed automata with urgent transitions. A necessary and sufficient condition, called complete urgency, is formulated and proved for avoiding zone partitioning so that the system state graphs are simpler and model checking is faster. A novel zone capping method is proposed that is time-reactive, preserves complete urgency, satisfies all deadlines, and does not need zone partitioning. The proposed verification methods were implemented in the SGM CTL model checker and applied to real-time and embedded systems. Several experiments, comparing the state space sizes produced by SGM with that by the IF toolset, show that SGM produces much smaller state-spaces.