Model checking
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Support for partial run-time reconfiguration of platform FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Software-controlled dynamically swappable hardware design in partially reconfigurable systems
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
A Reconfiguration-Aware Floorplacer for FPGAs
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Reconfigurable System Design and Verification
Reconfigurable System Design and Verification
Modeling and verification of real-time embedded systems with urgency
Journal of Systems and Software
From Reconfigurable Architectures to Self-Adaptive Autonomic Systems
CSE '09 Proceedings of the 2009 International Conference on Computational Science and Engineering - Volume 02
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture
Journal of Systems Architecture: the EUROMICRO Journal
Dynamic objects: Supporting fast and easy run-time reconfiguration in FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
pvFPGA: accessing an FPGA-based hardware accelerator in a paravirtualized environment
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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To facilitate the development of the dynamically partially reconfigurable system (DPRS), we propose a model-based platform-specific co-design (MPC) methodology for DPRS with hardware virtualization and preemption. For DPRS analysis and validation, a model-based verification and estimation framework is proposed to make model-driven architecture (MDA) more realistic and applicable to the DPRS design. Considering inherent characteristics of DPRS and real-time system requirements, a semi-automatic model translator converts the UML models of DPRS into timed automata models with transition urgency semantics for model checking. Furthermore, a UML-based hardware/software co-design platform (UCoP) can support the direct interaction between the UML models and the real hardware architecture. Compared to the existing estimation methods, UCoP can provide accurate and efficient platform-specific verification and estimation. We also propose a hierarchical design that consists of a hardware virtualization mechanism for dynamically linking the device nodes, kernel modules, and on-demand reconfigurable hardware functions and a hardware preemption mechanism for further increasing the utilization of hardware resources per unit time. Further, we realize a dynamically partially reconfigurable network security system (DPRNSS) to show the applicability and practicability of the MPC methodology. The DPRNSS cannot only dynamically adapt some of its hardware functions at run-time to meet different system requirements, but also determine which mechanism will be used. Our experiments also demonstrate that the hardware virtualization mechanism can save the overall system execution time up to 12.8% and the hardware preemption mechanism can reduce up to 41.3% of the time required by reconfiguration-based methods.