Design patterns: elements of reusable object-oriented software
Design patterns: elements of reusable object-oriented software
The swappable logic unit: a paradigm for virtual hardware
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Designing an Operating System for a Heterogeneous Reconfigurable SoC
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling
ACM Transactions on Embedded Computing Systems (TECS)
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Hardware task scheduling and placement in operating systems for dynamically reconfigurable SoC
Journal of Embedded Computing - Selected papers of EUC 2005
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Journal of Systems Architecture: the EUROMICRO Journal
A self-adaptive hardware/software system architecture for ubiquitous computing applications
UIC'10 Proceedings of the 7th international conference on Ubiquitous intelligence and computing
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We propose two basic wrapper designs and an enhanced wrapper design for arbitrary digital hardware circuit designs such that they can be enhanced with the capability for dynamic swapping controlled by software. A hardware design with either of the proposed wrappers can thus be swapped out of the partially reconfigurable logic at runtime in some intermediate state of computation and then swapped in when required to continue from that state. The context data is saved to a buffer in the wrapper at interruptible states, and then the wrapper takes care of saving the hardware context to communication memory through a peripheral bus, and later restoring the hardware context after the design is swapped in. The overheads of the hardware standardization and the wrapper in terms of additional reconfigurable logic resources and the time for context switching are small and generally acceptable. With the capability for dynamic swapping, high priority hardware tasks can interrupt low-priority tasks in real-time embedded systems so that the utilization of hardware space per unit time is increased.