Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead
Journal of VLSI Signal Processing Systems
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
An FPGA Interpreter with Virtual Hardware Management
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Multitasking on FPGA Coprocessors
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Stream Computations Organized for Reconfigurable Execution (SCORE)
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Virtual Hardware Handler for RTR Systems
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Fast Online Placement for Reconfigurable Computing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Preemptive Multitasking on FPGAs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Prerouted FPGA cores for rapid system construction in a dynamic reconfigurable system
EURASIP Journal on Embedded Systems
Modeling and design of fault-tolerant and self-adaptive reconfigurable networked embedded systems
EURASIP Journal on Embedded Systems
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Software-controlled dynamically swappable hardware design in partially reconfigurable systems
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Applying dynamic reconfiguration for fault tolerance in fine-grained logic arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Data Reallocation by Exploiting FPGA Configuration Mechanisms
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
ReconOS: Multithreaded programming for reconfigurable computers
ACM Transactions on Embedded Computing Systems (TECS)
Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Hardware JIT compilation for off-the-shelf dynamically reconfigurable FPGAs
CC'08/ETAPS'08 Proceedings of the Joint European Conferences on Theory and Practice of Software 17th international conference on Compiler construction
Dynamically reconfigurable system-on-programmable-chip
EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
The RecoBlock SoC platform: a flexible array of reusable run-time-reconfigurable IP-blocks
Proceedings of the Conference on Design, Automation and Test in Europe
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Swappable Logic Units (SLUs) were introduced by the author previously (1996) to play a role in virtual hardware subsystems that is analogous to the role of pages or segments in virtual memory subsystems. The intention is that a conventional operating system can be extended to manage SLU circuitry implemented using FPGA real estate. In order to minimise operating system overheads, two particular SLU-based virtual hardware models were deemed practical: a "sea of accelerators" model and a "parallel harness" model. This paper looks in some detail at how SLUs will fit within the overall environment of a fairly conventional hardware/software system. First, there is a discussion of the FPGA-based hardware environment for SLUs, followed by a discussion of the software environment from which SLUs might be used. After this, there is a description of the operational properties that SLUs can have, and how these fit in with the two virtual hardware models. Finally, proposals for standard interfaces between SLUs and their environment are discussed. These interfaces can be regarded as constraints on the designers of SLU circuitry or, more positively, as suppliers of an enriched context within which such circuitry operates. The overall impact of the work presented in the paper is to show that it is feasible to incorporate configurable hardware within traditional computer systems that use high-level language programs and computer operating systems. That is, it should not always be necessary to devise special-purpose hardware/software systems to realise custom computing.