PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
A Self-Reconfigurable Gate Array Architecture
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Stream Computations Organized for Reconfigurable Execution (SCORE)
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
The swappable logic unit: a paradigm for virtual hardware
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
The Design and Implementation of a Context Switching FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The NAPA Adaptive Processing Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Design and implementation of digital linear control systems on reconfigurable hardware
EURASIP Journal on Applied Signal Processing
Scalable MPEG-4 encoder on FPGA multiprocessor SOC
EURASIP Journal on Embedded Systems
Run-time integration of reconfigurable video processing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A process-driven computing model for reconfigurable semiconductor manufacturing
Robotics and Computer-Integrated Manufacturing
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Today's high-density FPGAs and intellectual property (IP) components enable the integration of complex systems in one programmable chip. New design strategies and concepts have to be developed in order to utilize the new system-level integration facilities. The approach introduced within this paper describes the implementation of a communication infrastructure that provides a number of on-chip IP-sockets. By using the FPGA-feature of partial dynamic reconfiguration, different IP components can be plugged into these sockets during runtime. This leads to a reconfigurable system that can be adapted to varying demands. In this context we designed a 32-bit RISC processor and an AMBA on-chip interconnection bus. Finally we mapped these components on a reconfigurable system-level FPGA. The resulting sizes and the utilization of the FPGA's resources are presented within the last part of this paper.