Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
String matching on multicontext FPGAs using self-reconfiguration
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Genetic Programming Using Self-Reconfigurable FPGAs
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
The Design and Implementation of a Context Switching FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
On the Communication Capability of the Self-Reconfigurable Gate Array Architecture
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Efficient Metacomputation Using Self-Reconfiguration
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Configuring the Circuit Switched Tree for Multiple Width Communications
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 8 - Volume 09
Hyperreconfigurable architectures and the partition into hypercontexts problem
Journal of Parallel and Distributed Computing
Dynamically reconfigurable system-on-programmable-chip
EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
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This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chip configuration/data memory. These two features are necessary for efficient self-reconfiguration and are useful in general as well--no other device offers both features. The enhanced context switching feature permits arbitrary regions of the chip to selectively context switch--its not necessary for the whole device to do so. The memory access feature allows data transfer between logic cells and memory locations, and also directly between memory locations. The key innovation enabling the above features is the use of a mesh of trees based interconnect with logic cells and memory blocks at the leaf nodes and identical switches at other nodes. The mesh of trees topology allows a logic cell to be associated with a pair of switches. The logic cell and the switches can be placed close to the memory block that stores their configuration bits. The physical proximity enables fast context switching while the mesh of trees topology permits fast memory access. To evaluate the architecture, a point design with 8 × 8 logic cells was synthesized using a standard cell library for a 0.25 µm process with 5 metal layers. Timing results obtained show that both context switching and memory access can be performed within a 10 ns clock cycle. Finally, this paper also illustrates how self-reconfiguration can be used to do basic routing operations of connecting two logic cells or inserting a logic cell by breaking an existing connection--algorithms (implemented as configured logic) to perform the above operations in a few clock cycles are presented.