Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
On the Communication Capability of the Self-Reconfigurable Gate Array Architecture
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Reconfigurable Mesh on the Reconfigurable Tree Array
PDPTA '02 Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications - Volume 3
A Self-Reconfigurable Gate Array Architecture
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Efficient Metacomputation Using Self-Reconfiguration
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Dynamic Reconfiguration: Architectures and Algorithms (Series in Computer Science (Kluwer Academic/Plenum Publishers).)
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Dynamically reconfigurable architectures offer extremely fast solutions to various problems. The Circuit Switched Tree (CST) is an important interconnect used to implement such architectures. A CST consists of processing elements (PEs) and switches. PEs communicate among themselves using the links of the tree. A key component for successful communication is scheduling individual communications and the configuration of the CST switches. This paper presents a scheduling and configuration algorithm for communications on a CST where conflicts force multiple rounds of routing to perform all communications. The paper also explains how to apply the algorithm to two important classes of communications, well-nested and monotonic, for which the algorithm is optimal and efficient. The algorithm is distributed and requires only local knowledge, yet it captures the global picture to ensure proper communication.