Dynamic Reconfiguration: Architectures and Algorithms (Series in Computer Science (Kluwer Academic/Plenum Publishers).)

Lower Bounds on the Loading of Multiple Bus Networks for Binary Tree Algorithms

IEEE Transactions on Computers

An Efficient R-Mesh Implementation of LDPC Codes Message-Passing Decoder

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 8 - Volume 09

Configuring the Circuit Switched Tree for Multiple Width Communications

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 8 - Volume 09

Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices

IEEE Design & Test

On communication models for algorithm design in networked sensor systems: A case study

Pervasive and Mobile Computing

The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer

Journal of VLSI Signal Processing Systems

Examining the Feasibility of Reconfigurable Models for Molecular Dynamics Simulation

ICA3PP '08 Proceedings of the 8th international conference on Algorithms and Architectures for Parallel Processing

IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration

Microelectronics Journal

Performance and power efficient on-chip communication using adaptive virtual point-to-point connections

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip

Relating the power of the Multiple Associative Computing (MASC) model to that of reconfigurable bus-based models

Journal of Parallel and Distributed Computing

Design of a simulator for mesh-based reconfigurable architectures

NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing

A hybrid packet-circuit switched on-chip network based on SDM

Proceedings of the Conference on Design, Automation and Test in Europe

simulating a PR-mesh on an larpbs

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing

A computationally efficient engine for flexible intrusion detection

IEEE Transactions on Very Large Scale Integration (VLSI) Systems