IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration

Authors:
José M. Granado;Miguel A. Vega-Rodríguez;Juan M. Sánchez-Pérez;Juan A. Gómez-Pulido
Affiliations:
Department Technologies of Computers and Communications, University of Extremadura, Spain;Department Technologies of Computers and Communications, University of Extremadura, Spain;Department Technologies of Computers and Communications, University of Extremadura, Spain;Department Technologies of Computers and Communications, University of Extremadura, Spain
Venue:
Microelectronics Journal
Year:
2009

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Abstract

In this work, we present our experience in implementing two different cryptographic algorithms in an FPGA: IDEA and AES. Both implementations have been done by means of mixing Handel-C and VHDL and using partial and dynamic reconfiguration in order to reach a very high performance. In both cases, we have obtained very satisfactory results, achieving 27.948Gb/s in the IDEA algorithm and 24.922Gb/s in the AES algorithm.