VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Applied cryptography (2nd ed.): protocols, algorithms, and source code in C
Applied cryptography (2nd ed.): protocols, algorithms, and source code in C
An FPGA implementation and performance evaluation of the Serpent block cipher
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
On Computing Multiplicative Inverses in GF(2/sup m/)
IEEE Transactions on Computers
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
Power-efficient ASIC synthesis of cryptographic sboxes
Proceedings of the 14th ACM Great Lakes symposium on VLSI
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
Microelectronics Journal
A secure digital camera architecture for integrated real-time digital rights management
Journal of Systems Architecture: the EUROMICRO Journal
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
Integration, the VLSI Journal
Full custom low-power/high performance DDP-based Cobra-H64 cipher
Computers and Electrical Engineering
Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications
Transactions on Data Privacy
FPGA implementation and performance evaluation of a high throughput crypto coprocessor
Journal of Parallel and Distributed Computing
NanoCMOS-molecular realization of rijndael
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Integration, the VLSI Journal
| Hi-index | 14.98 |
Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decryption process. They reduce the required hardware resources and achieve high-speed performance. Their design philosophy is completely different. The first uses feedback logic and reaches a throughput value equal to 259 Mbit/sec. It performs efficiently in applications with low covered area resources. The second architecture is optimized for high-speed performance using pipelined technique. Its throughput can reach 3.65 Gbit/sec.