Full custom low-power/high performance DDP-based Cobra-H64 cipher

Authors:
A. Rjoub;M. Mousameh;O. Koufopavlou
Affiliations:
Jordan University of Science and Technology, Faculty of Computer and Information Technology, Department of Computer Engineering, P.O. Box 3030, Irbid 22110, Jordan;Jordan University of Science and Technology, Faculty of Computer and Information Technology, Department of Computer Engineering, P.O. Box 3030, Irbid 22110, Jordan;University of Patras, Department of Electrical and Computer Engineering, VLSI Design Laboratory, Patras 26110, Greece
Venue:
Computers and Electrical Engineering
Year:
2010

Citing 14
Cited 0

Applied cryptography (2nd ed.): protocols, algorithms, and source code in C

Applied cryptography (2nd ed.): protocols, algorithms, and source code in C
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint

ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Low-Power CMOS Design

Low-Power CMOS Design
Architectures and VLSI Implementations of the AES-Proposal Rijndael

IEEE Transactions on Computers
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling

Proceedings of the 40th annual Design Automation Conference
Optimal Transistor Tapering for High-Speed CMOS Circuits

Proceedings of the conference on Design, automation and test in Europe
Leakage Current: Moore's Law Meets Static Power

Computer
High speed networking security: design and implementation of two new DDP-based ciphers

Mobile Networks and Applications
State of the Art in Ultra-Low Power Public Key Cryptography for Wireless Sensor Networks

PERCOMW '05 Proceedings of the Third IEEE International Conference on Pervasive Computing and Communications Workshops
Energy Scalable Universal Hashing

IEEE Transactions on Computers
Low-Power Processors and Systems on Chips

Low-Power Processors and Systems on Chips
Wireless Security and Cryptography: Specifications and Implementations

Wireless Security and Cryptography: Specifications and Implementations
64-bit Block ciphers: hardware implementations and comparison analysis

Computers and Electrical Engineering
An area-efficient universal cryptography processor for smart cards

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents, for the first time, a full custom layout design for a Data Dependent Permutation (DDP)-Cobra H64-bit cipher, using pipelining techniques in the internal rounds blocks to increase the throughput of the design. As a result, the silicon area and the power dissipation are reduced too. The design achieves a small area by simplifying the complex design by simpler designs. Low power consumption is satisfied by using low power logic gates. The throughput ranges from 5.5 to 8.4Gbps. Simulation results based on the layout level have confirmed the validity of the proposed technique, as well as have confirmed that low power, speed and performance can be optimized through design at the layout level.