More efficient software implementations of (generalized) DES
Computers and Security
Universal strong encryption FPGA core implementation
Proceedings of the conference on Design, automation and test in Europe
Cryptography: Theory and Practice
Cryptography: Theory and Practice
Unbalanced Feistel Networks and Block Cipher Design
Proceedings of the Third International Workshop on Fast Software Encryption
A Fast New DES Implementation in Software
FSE '97 Proceedings of the 4th International Workshop on Fast Software Encryption
A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Attacking the semantic gap between application programming languages and configurable hardware
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Architectures and VLSI Implementations of the AES-Proposal Rijndael
IEEE Transactions on Computers
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
ISC '01 Proceedings of the 4th International Conference on Information Security
Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512
ISC '02 Proceedings of the 5th International Conference on Information Security
A Dynamic FPGA Implementation of the Serpent Block Cipher
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Rijndael FPGA Implementations Utilising Look-Up Tables
Journal of VLSI Signal Processing Systems
Environment-independent performance analyses of cryptographic algorithms
ACSC '03 Proceedings of the 26th Australasian computer science conference - Volume 16
An Adaptive Cryptographic Engine for IPSec Architectures
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A reconfigurable logic-based processor for the SCAN image and video encryption algorithm
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
An adaptive cryptographic engine for internet protocol security architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
An Instruction-Level Distributed Processor for Symmetric-Key Cryptography
IEEE Transactions on Parallel and Distributed Systems
Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multigrid solvers in reconfigurable hardware
Journal of Computational and Applied Mathematics
A field programmable gate array media player for realmedia files
Journal of Computing Sciences in Colleges
Design of a novel hardware data structure for cryptographic applications
ACC'08 Proceedings of the WSEAS International Conference on Applied Computing Conference
The input-aware dynamic adaptation of area and performance for reconfigurable accelerator
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Parallel algorithms development for programmable devices with application from cryptography
International Journal of Parallel Programming
Hardware vs. software implementations for calculating roots of polynomials
Journal of Computing Sciences in Colleges
An efficient design of security accelerator for IEEE 802.15.4 wireless sensor networks
CCNC'10 Proceedings of the 7th IEEE conference on Consumer communications and networking conference
Architecture and operating system support for two-dimensional runtime partial reconfiguration
The Journal of Supercomputing
Clustering scheduling for hardware tasks in reconfigurable computing systems
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 0.00 |
With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Eneryption Standard (AES) development process is well underway. It is hoped that the result of the AES process will be the specification of a new non-classified encryption algorithm that will have the global acceptance achieved by DES as well as the capability of long-term protection of sensitive information. The technical analysis used in determining which of the potential AES candidates will be selected as the Advanced Encryption Algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of an FPGA implementation of Serpent, one of the Advanced Encryption Standard candidate algorithms. Multiple architecture options of the Serpent algorithm will be explored with a strong focus being placed on a high speed implementation within an FPGA in order to support security for current and future high bandwidth applications. One of the main findings is that Serpent can be implemented with encryption rates beyond 4 Gbit/s on current FPGAs.