On the security of multiple encryption
Communications of the ACM
Handbook of Applied Cryptography
Handbook of Applied Cryptography
An FPGA implementation and performance evaluation of the Serpent block cipher
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A 12 Gbps DES Encryptor/Decryptor Core in an FPGA
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
A Dynamic FPGA Implementation of the Serpent Block Cipher
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
A 155 Mbps Triple-DES Network Encryptor
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm)
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
High speed networking security: design and implementation of two new DDP-based ciphers
Mobile Networks and Applications
Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security
The Journal of Supercomputing
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The Sandia National Laboratories (SNL) Data Encryption Standard (DES) Application Specific Integrated Circuit (ASIC) is the fastest known implementation of the DES algorithm as defined in the Federal Information Processing Standards (FIPS) Publication 46-2. DES is used for protecting data by cryptographic means. The SNL DES ASIC, over 10 times faster than other currently available DES chips, is a high-speed, fully pipelined implementation offering encryption, decryption, unique key input, or algorithm bypassing on each clock cycle. Operating beyond 105 MHz on 64 bit words, this device is capable of data throughputs greater than 6.7 Billion bits per second (tester limited). Simulations predict proper operation up to 9.28 Billion bits per second. In low frequency, low data rate applications, the ASIC consumes less that one milliwatt of power. The device has features for passing control signals synchronized to throughput data. Three SNL DES ASICs may be easily cascaded to provide the much greater security of triple-key, triple-DES.