PGP source code and internals
The Twofish encryption algorithm: a 128-bit block cipher
The Twofish encryption algorithm: a 128-bit block cipher
JRoute: A Run-Time Routing API for FPGA Hardware
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
A case study of partially evaluated hardware circuits: Key-specific DES
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Evaluation of the XC6200-series Architecture for Cryptographic Applications
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
A High-Performance Flexible Architecture for Cryptography
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
DES Key Breaking, Encryption and Decryption on the XC6216
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Combined instruction and loop parallelism in array synthesis for FPGAs
Proceedings of the 14th international symposium on Systems synthesis
A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator
Proceedings of the 39th annual Design Automation Conference
Multipartite Tables in JBits for the Evaluation of Functions on FPGAs
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
JBitsTM Implementations of the Advanced Encryption Standard (Rijndael)
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A 12 Gbps DES Encryptor/Decryptor Core in an FPGA
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
A Dynamic FPGA Implementation of the Serpent Block Cipher
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis
IEEE Transactions on Computers
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
An HMAC processor with integrated SHA-1 and MD5 algorithms
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An Instruction-Level Distributed Processor for Symmetric-Key Cryptography
IEEE Transactions on Parallel and Distributed Systems
Examining the viability of FPGA supercomputing
EURASIP Journal on Embedded Systems
Efficient hardware implementations for the DES family
ISP'06 Proceedings of the 5th WSEAS International Conference on Information Security and Privacy
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
On the power consumption of security algorithms employed in wireless networks
CCNC'09 Proceedings of the 6th IEEE Conference on Consumer Communications and Networking Conference
Design and implementation of data encryption for networked control systems
SMC'09 Proceedings of the 2009 IEEE international conference on Systems, Man and Cybernetics
High-level synthesis with reconfigurable datapath components
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Enhancing the performance of symmetric-key cryptography via instruction set extensions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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A JBits implementation of the Data Encryption Standard (DES) algorithm in a Virtex FPGA is described. The Virtex architecture efficiently implements the DES primitive operations, and permits a high degree of pipelining. JBits provides a Java-base d Application Programming Interface (API) for the runtime creation and modification of the configuration bitstream. This allows dynamic circuit specialization based on a specific key and mode (encrypt or decrypt). The key schedule is computed entirely in software, and is part of the bitstream. As a result, all cryptographic key input and subkey generation logic are removed from the fully unrolled datapath. When combined with a speed efficient layout, the result is a throughput of over 10 Gigabits per second. This exceeds the performance of a recently announced DES ASIC.