More efficient software implementations of (generalized) DES
Computers and Security
Cipher Instruction Search Attack on the Bus-Encryption Security Microcontroller DS5002FP
IEEE Transactions on Computers
Efficient Software Implementation of AES on 32-Bit Platforms
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Fast New DES Implementation in Software
FSE '97 Proceedings of the 4th International Workshop on Fast Software Encryption
Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis
IEEE Transactions on Computers
High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm)
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A Fully Pipelined, 700MBytes/s DES Encryption Core
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
A Flip-Chip Implementation of the Data Encryption Standard (DES)
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
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Network data is, currently, often encrypted at a low level. In addition, as it is widely supported, the majority of future networks will use low-layer (IP level) encryption. Moreover, current trends imply that future networks are likely to be dominated by mobile terminals, thus, the power consumption and electromagnetic emissions aspects of encryption devices will be critical. This paper presents several realizations of one of the most widely used encryption algorithm, the DES/TripleDES, both in software and in hardware. We present software implementations of the algorithm running on two of the state-of-the-art Intel IXP network processors and several hardware realizations based on a standard-cell library. The hardware platforms presented appear to be optimal. Moreover, by placing and routing those designs, we have also realized that the commercial ASIC synthesis tools cannot accurately predict the area and the performance of the placed & routed final netlist in such designs, since the ASIC implementations of the encrypted algorithms include a very large number of wires and a limited number of logic CMOS cells.