Flexible processors: a promising application-specific processor design approach
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
Network and internetwork security: principles and practice
Network and internetwork security: principles and practice
An FPGA implementation and performance evaluation of the Serpent block cipher
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
IEEE Transactions on Computers
CryptoManiac: a fast flexible architecture for secure communication
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Handbook of Applied Cryptography
Handbook of Applied Cryptography
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
A case study of partially evaluated hardware circuits: Key-specific DES
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Unbalanced Feistel Networks and Block Cipher Design
Proceedings of the Third International Workshop on Fast Software Encryption
A High-Performance Flexible Architecture for Cryptography
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
The NAPA Adaptive Processing Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm)
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
A Dynamically Reconfigurable Architecture for Embedded Systems
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
Modeling and mapping for dynamically reconfigurable hybrid architectures
Modeling and mapping for dynamically reconfigurable hybrid architectures
Design principles for a virtual multiprocessor
Proceedings of the 2007 annual research conference of the South African institute of computer scientists and information technologists on IT research in developing countries
CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
ISTASC'09 Proceedings of the 9th WSEAS International Conference on Systems Theory and Scientific Computation
A partial image encryption method with pseudo random sequences
ICISS'06 Proceedings of the Second international conference on Information Systems Security
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Efficient implementation of block ciphers is critical toward achieving both high security and high-speed processing. Numerous block ciphers have been proposed and implemented, using a wide and varied range of functional operations. Existing architectures such as microcontrollers do not provide this broad range of support. Therefore, we will present a hardware architecture that achieves efficient block cipher implementation while maintaining flexibility through reconfiguration. In an effort to achieve such a hardware architecture, a study of a wide range of block ciphers was undertaken to develop an understanding of the functional requirements of each algorithm. This study led to the development of COBRA, a reconfigurable architecture for the efficient implementation of block ciphers. A detailed discussion of the top-level architecture, interconnection scheme, and underlying elements of the architecture will be provided. System configuration and on-the-fly reconfiguration will be analyzed, and from this analysis, it will be demonstrated that the COBRA architecture satisfies the requirements for achieving efficient implementation of a wide range of block ciphers that meet the 622 Mbps ATM network encryption throughput requirement.