Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
Design and implementation of the “Tiny RISC” microprocessor
Microprocessors & Microsystems
A reconfigurable VLSI coprocessing system for the block matching algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Design & Test
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
IEEE Transactions on Computers
An Instruction-Level Distributed Processor for Symmetric-Key Cryptography
IEEE Transactions on Parallel and Distributed Systems
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Abstract: Internet is becoming one of the key features of tomorrow's communication world. The evolution of mobile phones networks such as UMTS will soon allow everyone to be connected everywhere. These new network technologies bring the ability to deal not only with classical voice or text messages, but also with improved content: multimedia. At the mobile level, this kind of data oriented content requires highly efficient architectures; and nowadays embedded system-on-chip solutions will no longer be able to manage the critical constraints like area, power and data computing efficiency. In this paper we will propose a new dynamically reconfigurable network, dedicated to data oriented applications such as the one targeted for instance on third generation networks. Principles, realisations and comparative results will be exposed for some classical applications, targeted on different architectures.