Warp architecture and implementation
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
HORSE: a simulation of the horizon supercomputer
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Warp: an integrated solution of high-speed parallel computing
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
On high-speed computing with a programmable linear array
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
HGA: a hardware-based genetic algorithm
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
High-level bit-serial datapath synthesis for multi-FPGA systems
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A Real-Time Matching System for Large Fingerprint Databases
IEEE Transactions on Pattern Analysis and Machine Intelligence
A reconfigurable hardware approach to network simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Kestrel: A Programmable Array for Sequence Analysis
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Multi-terminal net routing for partial crossbar-based multi-FPGA systems
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Dynamically reconfigurable architecture for image processor applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IEEE Transactions on Computers
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Board-level multiterminal net assignment
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Adaptive interfacing with reconfigurable computers
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
General-Purpose Systolic Arrays
Computer
AnyBoard: An FPGA-Based, Reconfigurable System
IEEE Design & Test
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures
IEEE Transactions on Computers
Compiler Optimizations for Adaptive EPIC Processors
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Multiterminal net routing for partial crossbar-based multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Kestrel: Design of an 8-bit SIMD Parallel Processor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Reconfigurable Elements for a Video Pipeline Processor
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Parallelizing Applications into Silicon
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
VaWiRAM: a variable width random access memory module
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Routability improvement using dynamic interconnect architecture
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Run time reconfiguration of FPGA for scanning genomic databases
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Architecture of a FPGA-based coprocessor: the PAR-1
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
A Dynamically Reconfigurable Architecture for Embedded Systems
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
Board-level multiterminal net assignment for the partial cross-bar architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
The UCSC Kestrel Parallel Processor
IEEE Transactions on Parallel and Distributed Systems
Modeling instruction placement on a spatial architecture
Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
Finding the Next Computational Model: Experience with the UCSC Kestrel
Journal of Signal Processing Systems
Design, Debug, Deploy: The Creation of Configurable Computing Applications
Journal of Signal Processing Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Routability improvement using dynamic interconnect architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FMRPU: design of fine-grain multi-context reconfigurable processing unit
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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A two-slot addition called Splash, which enables a Sun workstation to outperform a Cray-2 on certain applications, is discussed. Following an overview of the Splash design and programming, hardware development is described. The development of the logic description generator is examined in detail. Splash's runtime environment is described, and an example application, that of sequence comparison, is given.