Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
Digital image processing (2nd ed.)
Digital image processing (2nd ed.)
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
A VLSI pyramid chip for multiresolution image analysis
International Journal of Computer Vision - Special issue: VLSI for computer vision
Digital Image Warping
Hierarchical Model-Based Motion Estimation
ECCV '92 Proceedings of the Second European Conference on Computer Vision
WACV '98 Proceedings of the 4th IEEE Workshop on Applications of Computer Vision (WACV'98)
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Cheops: a reconfigurable data-flow system for video processing
IEEE Transactions on Circuits and Systems for Video Technology
Very Large Scale Spatial Computing
UMC '02 Proceedings of the Third International Conference on Unconventional Models of Computation
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This paper describes a family of reconfigurable processing elements (RPEs) used to support video processing for the Sarnoff Vision Front End 200 (VFE-200) vision system. Within the VFE-200 RPEs have been used to estimate visual motion, compute 3D scene structure using stereo analysis, perform geo-metric transformations (warps) on imagery with interpolation, and to act as triple ported frame store memory units. The RPEs described in this paper in-corporate complex DRAM memory control interfaces, high precision fixed- and floating-point arithmetic (including floating point division), and sophisticated hybrids of memory and computational functions. Within this paper, the architecture and implementation of the RPEs and the VFE-200 are described, and examples of how the RPEs are used to support specific computer vision functions at real-time video rates are presented.