Parallel 2-D Convolution on a Mesh Connected Array Processor
IEEE Transactions on Pattern Analysis and Machine Intelligence
Parallel Algorithms for Image Template Matching on Hypercube SIMD Computers
IEEE Transactions on Pattern Analysis and Machine Intelligence
Two-Dimensional Convolution on a Pyramid Computer
IEEE Transactions on Pattern Analysis and Machine Intelligence
Efficient Parallel Algorithms for Image Template Matching on Hypercube SIMD Machines
IEEE Transactions on Pattern Analysis and Machine Intelligence
Convolution on Mesh Connected Multicomputers
IEEE Transactions on Pattern Analysis and Machine Intelligence
Decomposition methods for convolution operators
CVGIP: Graphical Models and Image Processing
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Systolic Processing and an Implementation for Signal and Image Processing
IEEE Transactions on Computers
Computer
Computer Vision Algorithms on Reconfigurable Logic Arrays
IEEE Transactions on Parallel and Distributed Systems
A Systolic Image Difference Algorithm for RLE-Compressed Images
IEEE Transactions on Parallel and Distributed Systems
Mapping a Single Assignment Programming Language to Reconfigurable Systems
The Journal of Supercomputing
A cluster-based geophysical template matching system
ACSC '01 Proceedings of the 24th Australasian conference on Computer science
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
Reconfigurable Elements for a Video Pipeline Processor
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Rigid molecule docking: FPGA reconfiguration for alternative force laws
EURASIP Journal on Applied Signal Processing
A reconfigurable computing framework for multi-scale cellular image processing
Microprocessors & Microsystems
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A Abstract: Convolution is a fundamental operation in many signal and image processing applications. Since the computation and communication pattern in a convolution operation is regular, a number of special architectures have been designed and implemented for this operator. The Von Neumann architectures cannot meet the real-time requirements of applications that use convolution as an intermediate step. We combine the advantages of systolic algorithms with the low cost of developing application specific designs using field programmable gate arrays (FPGAs) to build a scalable convolver for use in computer vision systems. The performance of the systolic algorithm of (Kung et al., 1981) is compared theoretically and experimentally with many other convolution algorithms reported in the literature. The implementation of a convolution operation on Splash 2, an attached processor based on Xilinx 4010 FPGAs, is reported with impressive performance gains.