Two-Dimensional Convolution on a Pyramid Computer
IEEE Transactions on Pattern Analysis and Machine Intelligence
A kernel-independent, pipelined architecture for real-time 2-D convolution
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A System Design/Scheduling Strategy for Parallel Image Processing
IEEE Transactions on Pattern Analysis and Machine Intelligence
Convolution on Mesh Connected Multicomputers
IEEE Transactions on Pattern Analysis and Machine Intelligence
Mesh and pyramid algorithms for iconic indexing
ICS '91 Proceedings of the 5th international conference on Supercomputing
Analysis of replicated data algorithms on processor array architectures
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Processor autonomy on SIMD architectures
ICS '93 Proceedings of the 7th international conference on Supercomputing
A multiprocessor DSP system using PADDI-2
DAC '98 Proceedings of the 35th annual Design Automation Conference
Parallel Image Correlation: Case Study to Examine Trade-Offs in Algorithm-to-Machine Mappings
The Journal of Supercomputing
A Sliding Memory Plane Array Processor
IEEE Transactions on Parallel and Distributed Systems
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
An efficient multiplier-less architecture for 2-D convolution with quadrant symmetric kernels
Integration, the VLSI Journal
An Efficient VLSI Architecture for Template Matching
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
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In this correspondence, a parallel 2-D convolution scheme is presented. The processing structure is a mesh connected array processor consisting of the same number of simple processing elements as the number of pixels in the image. For most windows considered, the number of computation steps required is the same as that of the coefficients of a convolution window. The proposed scheme can be easily extended to convolution windows of arbitrary size and shape. The basic idea of the proposed scheme is to apply the 1-D systolic concept to 2-D convolution on a mesh structure. The computation is carried out along a path called a convolution path in a systolic manner. The efficiency of the scheme is analyzed for windows of various shapes. The ideal convolution path is a Hamiltonian path ending at the center of the window, the length of which is equal to the number of window coefficients. The simple architecture and control strategy make the proposed scheme suitable for VLSI implementation.