A multiprocessor DSP system using PADDI-2

Authors:
Roy A. Sutton;Vason P. Srini;Jan M. Rabaey
Affiliations:
University of California, EECS Dept., Berkeley, CA;Data Flux Systems Inc., 1678 Shattuck Ave., MS 292, Berkeley, CA;University of California, EECS Dept., Berkeley, CA
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

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Abstract

We have integrated an image processing system built around PADDI-2, a custom 48 node MIMD parallel DSP. The system includes image processing algorithms, a graphical SFG tool, a simulator, routing tools, compilers, hardware configuration and debugging tools, application development libraries, and software implementations for hardware verification. The system board,connected to a SPARCstation via a custom Sbus controller, contains 384 processors in 8 VLSI chips. The software environment supports a multiprocessor system under development (VGI-1). The software tools and libraries are modular, with implementation dependencies isolated in layered encapsulations.