A multiprocessor DSP system using PADDI-2
DAC '98 Proceedings of the 35th annual Design Automation Conference
Transputers-Past, Present and Future
IEEE Micro
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
StrongARM: a high-performance ARM processor
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor
Proceedings of the 31st annual international symposium on Computer architecture
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Wavefront Array Processor: Language, Architecture, and Applications
IEEE Transactions on Computers
Computer
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the 2009 International Conference on Hybrid Information Technology
CGADL: an architecture description language for coarse-grained reconfigurable arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
A low-area multi-link interconnect architecture for GALS chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance programmable FPGA overlay for digital signal processing
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Modeling and Designing for Accuracy and Energy Efficiency in Wireless Electroencephalography Systems
ACM Journal on Emerging Technologies in Computing Systems (JETC)
QUKU: A dual-layer reconfigurable architecture
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Proceedings of the First International Workshop on Many-core Embedded Systems
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Many emerging and future applications require significant levels of complex digital signal processing and operate within limited power budgets. Moreover, dramatically rising VLSI fabrication and design costs make programmable and reconfigurable solutions increasingly attractive. The AsAP project addresses these challenges with a chip multiprocessor composed of simple processors with small memories, achieving high energy efficiency and throughput in a small chip area.