Lazy BTB: reduce BTB energy consumption using dynamic profiling
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Two new techniques integrated for energy-efficient TLB design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Configurable range memory for effective data reuse on programmable accelerators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A 32-bit 162 MHz/215 MHz custom VLSI ARM microprocessor is described. The chip contains two 16 Kbyte, 32-way set associative caches for instructions and data. The 2.1 M transistor chip is fabricated in a 2.0 V, 0.35 /spl mu/m, 3-layer metal CMOS process. It dissipates 0.5 W at 162 MHz/1.5 V and 1.1 W at 215 MHz/2.0 V.