Wavefront Array Processor: Language, Architecture, and Applications

Authors:
Sun-Yuan Kung;K. S. Arun;R. J. Gal-Ezer;D. V. Bhaskar Rao
Affiliations:
Department of Electrical Engineering-Systems, University of Southern California;-;-;-
Venue:
IEEE Transactions on Computers
Year:
1982

Citing 12
Cited 12

Can programming be liberated from the von Neumann style?: a functional style and its algebra of programs

Communications of the ACM
Introduction to VLSI Systems

Introduction to VLSI Systems
The Design and Analysis of Computer Algorithms

The Design and Analysis of Computer Algorithms
A preliminary architecture for a basic data-flow processor

ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
Asynchronous and clocked control structures for VLSI based interconnection networks

ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
VAL- ORIENTED ALGORITHMIC LANGUAGE, PRELIMINARY REFERENCE MANUAL

VAL- ORIENTED ALGORITHMIC LANGUAGE, PRELIMINARY REFERENCE MANUAL
Parallelism exposure and exploitation in programs

Parallelism exposure and exploitation in programs
The ILLIAC IV Computer

IEEE Transactions on Computers
ILLIAC IV Software and Application Programming

IEEE Transactions on Computers
Performance of a Simulated Dataflow Computer

IEEE Transactions on Computers
On the Number of Operations Simultaneously Executable in Fortran-Like Programs and Their Resulting Speedup

IEEE Transactions on Computers
Data Flow Supercomputers

Computer

Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays

IEEE Transactions on Computers
A Study of Pipelining in Computing Arrays

IEEE Transactions on Computers
A study of data interlock in computational networks for sparse matrix multiplication

IEEE Transactions on Computers
High Performance Multiprocessor Architecture Design Methodology for Application-Specific Embedded Systems

HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
AsAP: A Fine-Grained Many-Core Platform for DSP Applications

IEEE Micro
VLSI Array Design Under Constraint of Limited I/O Bandwidth

IEEE Transactions on Computers
Architecture and Evaluation of an Asynchronous Array of Simple Processors

Journal of Signal Processing Systems
A versatile VLSI fast Fourier transform processor

AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition
Microelectronic architectures and devices for signal and symbol processing

Integration, the VLSI Journal
VLSI architecture for device simulation

Integration, the VLSI Journal
Synthesis and array processor realization of a 2-D IIR beam filter for wireless applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Divergence analysis

ACM Transactions on Programming Languages and Systems (TOPLAS)

Quantified Score

Hi-index	14.99

Visualization

Abstract

This paper describes the development of a wavefront-based language and architecture for a programmable special-purpose multiprocessor array. Based on the notion of computational wavefront, the hardware of the processor array is designed to provide a computing medium that preserves the key properties of the wavefront. In conjunction, a wavefront language (MDFL) is introduced that drastically reduces the complexity of the description of parallel algorithms and simulates the wavefront propagation across the computing network. Together, the hardware and the language lead to a programmable wavefront array processor (WAP). The WAP blends the advantages of the dedicated systolic array and the general-purpose data-flow machine, and provides a powerful tool for the high-speed execution of a large class of matrix operations and related algorithms which have widespread applications.