Iterative solution of nonlinear equations in several variables
Iterative solution of nonlinear equations in several variables
Introduction to VLSI Systems
Wavefront Array Processor: Language, Architecture, and Applications
IEEE Transactions on Computers
VLSI Array Design Under Constraint of Limited I/O Bandwidth
IEEE Transactions on Computers
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In this paper, VLSI architectures for solving nonlinear equations are presented, such as the elliptic partial differential equations arising from semiconductor device modeling using a Newton-SOR (Successive Over Relaxation), finite difference, iterative scheme. The computation time for the matrix inversion using these pipeline array structures is O(m) instead of O(m^2) units required on a sequential machine, where m is the number of grid points in a particular coordinate direction. The much lower number of processing elements required in this approach simply means that these array structures can easier be implemented on a chip than those using direct methods. The architectures of the chips suitable for two-dimensional and three-dimensional device simulation are illustrated in this paper. They can equally apply to the solution of some other nonlinear equations such as the ones in circuit simulation, process simulation and some other engineering analyses, provided that a successive type of algorithm such as SOR is used, so that the data can be pipelined and the equations can be solved more efficiently than by a sequential machine.