VLSI Array Design Under Constraint of Limited I/O Bandwidth

Authors:
P. S. Liu;T. Y. Young
Affiliations:
Department of Electrical and Computer Engineering, University of Miami;-
Venue:
IEEE Transactions on Computers
Year:
1983

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Abstract

VLSI computing arrays for matrix multiplication and covariance matrix inversion have applications in many fields. Under the constraint of limited I/O bandwidth of the host system or the computing array, three configurations for the interfacing and controlling of a multiplication array to achieve optimal performance under different adverse situations are examined. The three configurations are multiplexing loading, processor row loading, and processor column group loading. A properly chosen configuration can significantly reduce the computing time of the multiplication array.