Sorting on a mesh-connected parallel computer
Communications of the ACM
The effect of VLSI on computer architecture
ACM SIGARCH Computer Architecture News
VLSI Array Design Under Constraint of Limited I/O Bandwidth
IEEE Transactions on Computers
On minimizing memory in systolic arrays for the dynamic time warping algorithm
Integration, the VLSI Journal
ICEC'10 Proceedings of the 9th international conference on Entertainment computing
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Pattern matching by dynamic time warp has recently been widely applied in the fields of speech and visual pattern recognition. A new approach to this technique that is based on an orthogonal array of simple processing elements is presented. The approach emphasizes using parallel computation and pipelined data flow to achieve extremely high throughput. The internal architecture of the basic processing element and an integrated CMOS implementation are described. Simulation estimates indicate performance gains of up to 200:1 over existing techniques.